Optical Die-to-Die at 1 Tb/s/mm: Qualcomm, Lumentum, and Corning at ECOC 2026

On September 21, 2026, Qualcomm Technologies, Lumentum, and Corning announced a joint board-level demonstration at ECOC 2026 in Málaga, Spain: a massively parallel optical die-to-die interconnect running at 32 Gb/s NRZ over Corning multimode fiber, using Qualcomm’s D2D interface IP and Lumentum’s 1060 nm VCSEL optical engine. The architecture targets approximately 1 Tb/s/mm of shoreline bandwidth density today, with a stated path to approximately 4 Tb/s/mm through higher lane rates and increased channel density.

The significant part is not the individual components. VCSELs, multimode fiber, and die-to-die interfaces each exist separately. The significant part is the combination: a D2D-class interface, designed for tight chip-to-chip coupling, connected directly to an optical engine and run over fiber spanning tens of meters. That combination asks whether the architectural boundary between a tightly coupled computer and a networked cluster can move.

Why Electrical D2D Has a Hard Reach Limit

Die-to-die interfaces such as UCIe deliver high bandwidth density and low latency by operating over short electrical traces, typically on the same package or board. The physics of electrical signaling imposes a reach limit: beyond a few centimeters, signal integrity degrades and power consumption climbs as drivers fight the losses in copper traces. This constraint is one reason why today’s AI accelerator systems have a strong physical hierarchy.

Inside a package, chiplets talk to each other through high-density electrical D2D links with bandwidths in the terabits-per-second range and latencies in the nanosecond range. Across board boundaries, the interconnect shifts to conventional pluggable optics with different latency and bandwidth-density characteristics. Across rack boundaries, scale-out networking takes over with its own latency and topology constraints. Each boundary is a sharp cliff in interconnect economics.

The consequence is that AI systems today are designed around those cliffs. The largest electrical package you can build becomes the atomic unit of scale-up compute. Everything beyond that package boundary is scale-out, with different programming models, collective communication patterns, and tolerance for latency. Building a larger logical system requires bridging those different domains explicitly in the software stack.

The Three-Party Architecture

The demonstration combines three distinct contributions. Qualcomm Technologies supplies the die-to-die interface IP subsystem, which Tony Chan Carusone, SVP Technology at Qualcomm Technologies, describes as designed to “optimize power and area while enabling efficient direct-drive optical connectivity and preserving the benefits of high bandwidth density and low power.” The Qualcomm D2D interface drives the optical engine directly without an intermediate electrical retimer, which is what enables the low-latency claim.

Lumentum supplies the optical engine: an advanced-packaged module based on 1060 nm VCSEL technology with approximately 10 Tb/s of aggregate transmit and receive capacity. The engine uses high-density two-dimensional VCSEL and photodetector arrays with backside lens technology. Matt Sysak, Chief Technology Officer at Lumentum, states: “By combining advanced VCSEL packaging with Qualcomm Technologies’ D2D interface technology and Corning’s fiber connectivity, we are showing a practical path toward compact, energy-efficient optical D2D links for next-generation AI scale-up architectures.”

Corning supplies multimode fiber glass ferrules for the high-density fiber connectivity. Claude Echahamian, Vice President and General Manager at Corning Optical Communications, identifies fiber density as the constraint that this work addresses: “As optical links move closer to compute devices, fiber connectivity must support increasing density, precision, and scalability.”

The proof-of-concept configuration uses 32 Gb/s NRZ channels, which is the current demonstration data rate. The architecture is designed to scale through higher channel counts and increasing per-lane data rates, which is how the path to 4 Tb/s/mm is described. The Lumentum optical engine’s approximately 10 Tb/s aggregate capacity defines the optical throughput headroom above the current 1 Tb/s/mm demonstration configuration.

What 1 Tb/s/mm Shoreline Density Means

Shoreline bandwidth density is the metric that matters for this class of demonstration, not raw aggregate bandwidth. It measures how much bandwidth can be delivered along a millimeter of package or board edge. High shoreline density means more interconnect bandwidth without a proportional increase in package size.

For context: conventional pluggable optics today deliver bandwidth densities measured in tens of gigabits per second per millimeter. The 1 Tb/s/mm target here is approximately one to two orders of magnitude higher, which is why the VCSEL approach uses two-dimensional arrays rather than a linear arrangement. The backside lens technology is part of what enables that 2D array density in a format compatible with board-level integration.

The path to 4 Tb/s/mm requires both higher per-lane data rates (above 32 Gb/s NRZ) and increased channel density in the VCSEL array. Neither of these is demonstrated in the current proof of concept, but both are within the roadmap of existing photonic packaging technology, which is why Lumentum describes this as a “line of sight” rather than a research goal.

The demonstration targets future co-packaged optics (CPO) and near-packaged optics (NPO) implementations, as well as emerging D2D interfaces such as UCIe. CPO places the optical engine physically adjacent to the compute die; NPO places it nearby on the board. Both remove the pluggable transceiver from the path, reducing per-bit power and allowing the higher shoreline density that two-dimensional VCSEL arrays provide. The Lumentum announcement is intended to show that the optical engine for this integration exists and works at the D2D interface level.

Limitations and Open Questions

The demonstration is a proof of concept, not a production interconnect. The announcement is a joint company statement, not a peer-reviewed paper with independently measured latency, power, and bit-error-rate results across operating conditions. The specific latency and power numbers for the Qualcomm-Lumentum-Corning combination are not reported in the announcement; the claim of “low latency and power consumption” is stated but not quantified.

Optical D2D and co-packaged optics are not new concepts. Coherent demonstrated multiple CPO technologies at OFC 2026, and the broader industry roadmap has placed switch-side CPO in the 2025-2026 period and compute-side optical I/O in 2027 and beyond. What the Lumentum-Qualcomm-Corning work adds is a concrete integrated demonstration at the D2D interface level using VCSEL technology built on Lumentum’s 3D sensing manufacturing base, which addresses the volume-manufacturing question that has been a longstanding concern for CPO adoption.

Whether the optical engine can preserve D2D-class signaling semantics at tens-of-meter reach under real system conditions, including thermal variation and vibration in production rack environments, remains the important question. The demonstration runs in a controlled show-floor environment. The path from proof-of-concept to a shipping interconnect involves qualification across operating conditions that a conference demonstration cannot represent.

The 32 Gb/s NRZ channel rate also represents a conservative starting point. 100G and 200G per-lane rates are already standard in data-center optics. Demonstrating D2D-class optical connectivity at those rates will be the next relevant benchmark, because the shoreline density improvement from 1 Tb/s/mm to 4 Tb/s/mm depends primarily on lane-rate scaling.

What This Means for Engineering Teams

The near-term implication is about infrastructure planning for AI systems, not about hardware you can buy today. Optical D2D connectivity at CPO/NPO density levels would allow accelerator fabric designs that are not constrained to the package boundary for scale-up bandwidth. A cluster of compute elements connected by optical D2D links could share memory-side bandwidth and collective communication bandwidth at a density that current pluggable optics cannot match.

For teams building large-scale AI model infrastructure, the relevant question is how much of the current system topology is shaped by the reach limits of electrical D2D versus actual software architecture preferences. Systems designed around tightly coupled electrical packages and loosely coupled network scale-out reflect the physics of today’s interconnect, not necessarily the ideal structure for the workloads.

The distributed inference pattern is a concrete case. Today, distributing a model across physical packages requires crossing the electrical-to-optical boundary with all the associated latency and bandwidth asymmetry. If optical D2D reaches tens-of-meter spans at shoreline densities approaching CPO levels, the programming model for distributed inference could resemble single-machine tensor parallelism rather than multi-node data parallelism. Teams working on distributed LLM architectures will recognize the significance: the synchronization overhead that currently dominates multi-node training is largely a consequence of interconnect topology, not of the distributed computation itself.

The production timeline for CPO at compute-side integration sits in the 2027-and-beyond window according to current industry roadmaps. Teams procuring infrastructure in 2026 are buying into the current electrical D2D and pluggable optics regime. But the procurement decisions made in the 2026-2027 window will shape infrastructure that runs for three to five years, which means the optical D2D roadmap is relevant to architecture decisions being made now even if the hardware is not yet shipping. AI infrastructure consulting that does not account for this interconnect transition will produce recommendations with a shorter useful life than the infrastructure they specify.

Key Takeaways

The Qualcomm-Lumentum-Corning ECOC 2026 demonstration runs Qualcomm D2D interface IP through a 1060 nm VCSEL optical engine over Corning multimode fiber at 32 Gb/s NRZ per channel.
The architecture targets approximately 1 Tb/s/mm shoreline bandwidth density today, with a stated path to approximately 4 Tb/s/mm through higher lane rates and increased channel density.
Lumentum’s optical engine provides approximately 10 Tb/s aggregate transmit and receive capacity using 2D VCSEL and photodetector arrays with backside lens technology.
The architecture is designed for future CPO and NPO implementations supporting UCIe-class D2D interfaces over optical links spanning tens of meters.
The demonstration is a proof of concept; latency, power, and bit-error-rate results across production operating conditions are not reported in the announcement.
Industry roadmaps place compute-side CPO integration in 2027 and beyond; the electrical D2D and pluggable optics regime remains the procurement reality for 2026 infrastructure.

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